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Five power vias and four ground vias are analyzed in this model of a power distribution portion of a printed circuit board. A small wire at the top of the structure is used to short circuit the vias, creating a large power flow to simulate a large load scenario. Power is supplied uniformly around the perimeter of the model via a current source (shown in yellow) for each power tab (shown in blue).
The full complexity of the interior of the circuit board has been included. This large mesh requires over 200 megabytes of memory to simulate. The time-domain response of the current draw is used to calculate the inductance of the overall structure.
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Calculation of the inductance |
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Java wire frame model (180 kb) |
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VRML model |
Copyright © Cray Inc.
